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<title>VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory </title></head>
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<h1>VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F38.W1 88 /r</p>
<p>VEXPANDPD xmm1 {k1}{z}, xmm2/m128</p></td>
<td>T1S</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Expand packed double-precision floating-point values from xmm2/m128 to xmm1 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F38.W1 88 /r</p>
<p>VEXPANDPD ymm1 {k1}{z}, ymm2/m256</p></td>
<td>T1S</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Expand packed double-precision floating-point values from ymm2/m256 to ymm1 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F38.W1 88 /r</p>
<p>VEXPANDPD zmm1 {k1}{z}, zmm2/m512</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Expand packed double-precision floating-point values from zmm2/m512 to zmm1 using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Expand (load) up to 8/4/2, contiguous, double-precision floating-point values of the input vector in the source operand (the second operand) to sparse elements in the destination operand (the first operand) selected by the writemask k1.</p>
<p>The destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.</p>
<p>The input vector starts from the lowest element in the source operand. The writemask register k1 selects the desti-nation elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed, depending on EVEX.z.</p>
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p>Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector.</p>
<p><strong>Operation</strong></p>
<p><strong>VEXPANDPD (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>k (cid:197) 0</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>DEST[i+63:i] (cid:197) SRC[k+63:k];</p>
<p>k (cid:197) k + 64</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197)(cid:3)0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VEXPANDPD __m512d _mm512_mask_expand_pd( __m512d s, __mmask8 k, __m512d a);</p>
<p>VEXPANDPD __m512d _mm512_maskz_expand_pd( __mmask8 k, __m512d a);</p>
<p>VEXPANDPD __m512d _mm512_mask_expandloadu_pd( __m512d s, __mmask8 k, void * a);</p>
<p>VEXPANDPD __m512d _mm512_maskz_expandloadu_pd( __mmask8 k, void * a);</p>
<p>VEXPANDPD __m256d _mm256_mask_expand_pd( __m256d s, __mmask8 k, __m256d a);</p>
<p>VEXPANDPD __m256d _mm256_maskz_expand_pd( __mmask8 k, __m256d a);</p>
<p>VEXPANDPD __m256d _mm256_mask_expandloadu_pd( __m256d s, __mmask8 k, void * a);</p>
<p>VEXPANDPD __m256d _mm256_maskz_expandloadu_pd( __mmask8 k, void * a);</p>
<p>VEXPANDPD __m128d _mm_mask_expand_pd( __m128d s, __mmask8 k, __m128d a);</p>
<p>VEXPANDPD __m128d _mm_maskz_expand_pd( __mmask8 k, __m128d a);</p>
<p>VEXPANDPD __m128d _mm_mask_expandloadu_pd( __m128d s, __mmask8 k, void * a);</p>
<p>VEXPANDPD __m128d _mm_maskz_expandloadu_pd( __mmask8 k, void * a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type E4.nb.</p>
<table>
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>